1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to programming the behavior of individual chips, or strata in a 3D stack of integrated circuits.
2. Description of the Related Art
To construct a 3D (i.e., multiple stratum) stacked integrated circuit (IC), it is desirable to first test individual chips before joining them into a 3D stack. However, the off-stratum inputs and outputs (I/Os) that must operate while an unstacked stratum (chip) is being tested may be different from the I/Os that must operate when the stratum is in a stack. A similar situation can exist for the clock source. While each chip may need its own clock source for test, the clock source in a stack may come from one selected stratum. Also, it may be desirable to make the stack out of functionally or physically equivalent chips that may differ only in their address assignment. For example, while a stacked memory integrated circuit may functionally include identical memory chips, the activation of a particular stratum would depend on the address accessed. A cost savings can be realized if these memory dies are physically identical.
One solution to the test/operation problem could be to provide separate stack I/Os that correspond to a set of control I/O pins, or data I/O pins connected in the stack with inclined through-Silicon via (TSV) connections such that each individual stratum remained accessible, from C4's or pads or other off-stack connection, once the stack was built. The values on these control pins could be set by the package wiring to “personalize” the stack. However, this solution requires a large number of stack I/O's and a large number of inclined TSVs, especially when stacking multiple strata. Inclined TSVs are disclosed in the aforementioned application entitled “Configuration of Connections in a 3D Stack of Integrated Circuits”, having U.S. application Ser. No. 13/217,789.